Draft: Conditional register syntax

Using an enable signal for a register is a very common pattern, e.g. when using a clock divider.

it can be expressed in spade as

reg(clk) gated: bool = {
    if clk_en {
        ...
    } else {
        gated
    }
};

However, when using multiple registers this gets boilerplaty quickly and it was something that slightly annoyed me about Verilog and VHDL.

Spade already supports syntax for conditional pipeline stages: reg[condition];

So, more concerned with whether I could than whether I should, I implemented this syntax for regular registers:

reg(clk)[clk_en] gated: bool = {
    ...
};

This is more of a suggestion and I am not sure whether this is even a good idea

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• a050182c - fix formatting

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Ohh, thanks for taking the time to implement this!

I'm a little bit torn on if this is a good idea or not. As you say, this is a common pattern that can get tedious at times. On the other hand, the reg syntax is already quite hard to read and understand if you're not used to it, and throwing in additional symbols doesn't make it easier.

I think that last part may be made better by perhaps using if <gate> instead of [condition], i.e.

reg(clk) gated: bool if clk_en = {
    ...
};

This way you can at least make a guess as to what the code does without reading docs.

That is indeed much easier to read. Would be easy enough to change. However this syntax could clash with the other register "attributes" and might look a little confusing:

reg(clk) gated: bool if condition initial(foo) = ...

Another alternative would be to simply do this:

reg(clk) gated: bool enable(condition) initial(foo) = ...

Enable does look very nice and clean! It's a bit annoying having to add another keyword to the language though :/ Especially for something that is mostly syntactic sugar for a specific case

Fair point. Might be more effort than it's worth.

how about this?

reg(clk) gated: bool if(condition) initial(foo) = ...

I'm going to close this because I don't think we're going to change the syntax until I do clock domain stuff soon

closed