Draft: Conditional register syntax (!292) · Merge requests · spade-lang / spade

Using an enable signal for a register is a very common pattern, e.g. when using a clock divider.

it can be expressed in spade as

reg(clk) gated: bool = {
    if clk_en {
        ...
    } else {
        gated
    }
};

However, when using multiple registers this gets boilerplaty quickly and it was something that slightly annoyed me about Verilog and VHDL.

Spade already supports syntax for conditional pipeline stages: reg[condition];

So, more concerned with whether I could than whether I should, I implemented this syntax for regular registers:

reg(clk)[clk_en] gated: bool = {
    ...
};

This is more of a suggestion and I am not sure whether this is even a good idea

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