Add simple automatic enum based clock gating
A decent chunk of chip energy usage is caused by signals switching from 1 to 0. It can be mitigated by keeping previous values in registers when they are unused. Normally this is done manually, but since we know which signals enable registers storing enums, we can do it manually in Spade.
This is an initial implementation of that idea, that is hard coded for the Option type and can be used to get an idea of the usefulness.
I also added an optimize attribute which can be added to modules to optimize them using specific passes. This isn't really meant to be used in practice, but it is useful if we want to test passes in the swim_test_project without changing configuration or passing flags around
Author checklist
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New Diagnostics have at least one snapshot test that triggers it -
Added a line to CHANGELOG.md, if relevant
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requested review from @sornas
swim_tests/test/enum_gating.py 0 → 10064417 clk, 18 period=10, 19 units='ns' 20 ).start()) 21 22 await FallingEdge(clk) 23 s.i.x = "Some(10)" 24 s.i.rst = "false" 25 await FallingEdge(clk) 26 s.o.cooked.assert_eq("Some(10)") 27 s.o.raw.assert_eq("0b1_0000_1010") 28 29 s.i.x = "None()" 30 await FallingEdge(clk) 31 s.o.cooked.assert_eq("None()") 32 # With the optimization turned on, the lsbs keep their previous values 2759 2759 2760 2760 build_and_compare_entities!(code, expected); 2761 2761 } 2762 2763 snapshot_error! { 2764 unknown_optimization_pass_is_an_error, 2765 " 2766 #[optimize(banana)] 2767 entity a() {} 2768 " 2769 } enabled an automatic merge when all merge checks for dcb219d1 pass