SystemVerilog

Signal generator 50 MHz

Custom UART IP core

Python Register InterFace Translation

Containerized FlexLM license manager for Questa*-Intel® FPGA Edition Software.

Containerized Questa*-Intel® FPGA Edition Software.

Repositorio grupal DVVSD P2021

Repositorio Personal DVVSD P2021

Toolchain for simulating and building FPGA projects.

A Docker image with the ModelSim HDL simulator

My repo for work on lecture Digital Hardware Design (WS 19/20, Prof Dr Bruening)